1. Technical Field of the Invention
This invention relates generally to digital circuitry and more in particular to differential digital circuitry.
2. Description of Related Art
Digital logic circuits, such as AND gates, NAND gates, NOR gates, OR gates, exclusive OR gates, latches, inverters, flip-flops, et cetera, are known to be used in a wide variety of electronic devices. For instance, digital logic circuits are used in all types of computers (e.g., laptops, personal computers, personal digital assistants, Internet, infrastructure equipment, telecommunication infrastructure equipment, et cetera), entertainment equipment (e.g., receivers, televisions, et cetera), and wireless communication devices (e.g., cellular telephones, radios, wireless local area networks, et cetera).
Typically, digital logic circuits are part of a larger circuit, which is fabricated as an integrated circuit. For example, a local oscillator within a radio frequency transmitter and/or receiver includes a plurality of flip-flops in its divider feedback section to provide adjustable divider values. As is known, by adjusting the divider value in a local oscillator, the resulting local oscillation can be adjusted to desired values.
As is also known, high performance applications, such as a radio frequency transmitter/receiver integrated circuit (IC), use differential signaling throughout the signal path to improve noise immunity. Accordingly, the circuits processing the differential signaling are differential circuits. For digital differential circuits, including digital logic circuits, a differential clock is needed to produce a 2-phase clock signal. Ideally, the two phases of the clock are complimentary (i.e., the inverse of each other) such that digital differential circuits produce complimentary output data. In practice, however, an ideal differential clock that has perfect complimentary phases is impossible to achieve due to component mismatches, IC process variations, et cetera, which result in rise and fall time mismatches of the 2 phases.
In lower rate applications, these mismatches are negligible and digital differential circuits clocked thereby operate sufficiently well. However, as the operating rates increase to the limits of integrated circuit fabrication processes (e.g., CMOS, gallium arsenide, silicon germanium), the mismatches are no longer negligible and, as such, digital differential circuits produce non-complimentary differential outputs, which leads to erroneous output values. Such errors are exasperated when the digital differential circuits are cascaded together, when the differential clock is passed through several inverter stages, or when the differential clock drives large loads.
Therefore, a need exists for a digital differential circuit for use in a high performance application, such as a radio frequency integrated circuit, that is insensitive to non-complimentary differential clocks and produces accurate complimentary digital outputs.